High technology components often suffer from an “infant mortality” problem. The components have a higher failure rate soon after being placed in service, followed by a decreased failure rate for the duration of the components' useful life. That is, if a device is going to fail, it is more likely to do so early in its useful life. These early failures can have a variety of causes, including bulk material defects and manufacturing variances. Burn-in testing is often performed to identify the components that will fail early on. The devices that survive the burn-in testing without failure can be expected to survive their useful life.
Burn-in testing generally involves utilizing the device for its intended purpose, or sometimes applying harsher than anticipated conditions for a period of time. The devices may be subject to increased heat, voltage or current, or may simply be operated according to their normal operating parameters.
Burn-in testing can be time-consuming and expensive. For example, to test an array of memory cells, data must be written to and read from the cells in the array using data test signals and a test clock signal. During testing, a test unit can apply and receive data signals to all of the data terminals of one or more memory device. However, the test unit can simultaneously test a larger number of memory devices if it applies data signals to and receives data signals from only some of the data terminals. Accordingly, compression testing is typically performed during burn-in of memory devices. In compression testing, burn-in test signals are applied only to a portion of the eternally-accessible data terminals. The memory device uses internal test mode circuitry to internally map the externally provided test signals to multiple memory cells within the device. The device then can internally map the external signals to cells in the memory array in addition to the memory cells that normally receive the data signals for a given address. The remaining externally-accessible data terminals “upstream” from where the data signals are mapped are decoupled from the memory cells and are held in the same state, usually a supply voltage VCC or ground, throughout the burn-in testing process. Similarly, read signals are applied to only a portion of the externally-accessible data terminals and then internally mapped to multiple memory cells within the device. Internal test mode circuitry then compares the read data, and sets an internal flag if an error is encountered. Each device is then interrogated for the presence of a flag. This allows more memory devices to go through burn-in testing in less time.